1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to a device structure to prevent a reduction in breakdown voltage of a power semiconductor device which has a trench MOS gate where a channel is formed in a surface of a trench buried in a semiconductor substrate, and to a method of manufacturing the device.
2. Description of the Background Art
FIG. 50 is a cross-sectional view of an insulated gate semiconductor device in a background art. Referring to this figure, now a vertical MOS (metal oxide semiconductor) transistor (hereinafter referred to as "UMOS") of a trench-gate structure will be discussed as an example. This UMOS is used for low breakdown voltage of 200 V or below, for example, used for an electrical equipment system of an automobile.
FIG. 50 shows an N.sup.+ substrate 1, an N.sup.- layer 2, a P base layer 3, an N.sup.+ source region 4, a trench 5, a gate insulating film 6, a gate 7, an interlayer insulating film 8, a source electrode 9, a drain electrode 10 and a channel region 11. Reference character L represents a spacing between the adjacent trenches.
Next, an operation of the UMOS will be discussed. When a prescribed drain voltage V.sub.DS is applied across the source electrode 9 and the drain electrode 10 and a prescribed gate voltage V.sub.GS is applied across the source electrode 9 and the gate 7, the channel region 11 of the P base layer 3 in the vicinity of the gate insulating film 6 is inverted to N type, thus forming a path for electric charges, i.e., a channel. The channel produces continuity between the source and drain, and the resistance of the UMOS produced at this time is called an ON-resistance.
In an On state, that is, a state where there is continuity between the source and drain, if the gate voltage V.sub.GS applied across the source electrode 9 and the gate 7 is changed to 0 V or a negative voltage, i.e., reverse bias, the gate is turned off and the channel region 11 of N type is inverted again to P type, entering an OFF state where there is no continuity between the source and drain. Thus, the control over the gate voltage V.sub.GS makes it possible to control a current flow between the source and drain, and therefore the UMOS can be used as a power switching device.
The drain voltage V.sub.DS applied to the UMOS when the gate is in the OFF state is referred to as a breakdown voltage of a device. The breakdown voltage of a device is generally determined by an impurity concentration and thickness of the N.sup.- layer 2 and in the case of the UMOS, further depends on a structure of a surface region of the device. Especially in the UMOS of trench structure, since the trench 5 protrudes into the N.sup.- layer 2 through the P base layer 3, the breakdown voltage of the device is dependent on the condition of a tip portion of the trench 5 protruding into the N.sup.- layer 2.
FIG. 51 is a simulation graph showing an electric field of the UMOS of trench structure. In the simulation, it is assumed that the impurity concentration of the N.sup.- layer 2 is 1 .OMEGA.cm and the thickness from a surface of the P base layer 3 to a bottom surface of the N.sup.- layer 2 is 8.5 .mu.m. The upper-left rectangular portion of FIG. 51 represents a portion of trench structure.
As can be seen form FIG. 51, when the drain voltage V.sub.DS is applied to the UMOS, a depletion region extends from the P base layer 3 to the N.sup.- layer 2, but the equipotential lines form loops to be discontinuous at the portion where the trench 5 protrudes into the N.sup.- layer 2, indicating that the electric field becomes stronger at the tip end portion of the trench 5. The breakdown voltage of the device depends on the electric field strength at the tip end portion.
The breakdown voltage of the device, which is dependent on a condition of the tip end portion of the trench 5, undergoes a more strict situation when the gate voltage V.sub.GS is changed into the reverse bias.
Specifically, the sum of the drain voltage V.sub.DS applied to the UMOS and the reverse-biased gate voltage V.sub.GS is applied to the tip portion of the trench 5 protruding into the N.sup.- layer 2. Accordingly, the breakdown voltage of the device when the gate voltage V.sub.GS is reversely biased is lower by a reverse-bias of the gate voltage V.sub.GS as compared with the case where the gate voltage V.sub.GS is 0 V.
As a countermeasure for reduction in breakdown voltage of the UMOS having trench structure, for example, a proposed device structure is disclosed in U.S. Pat. No. 5,072,266.
FIG. 52 is a cross-sectional perspective view of the device disclosed in U.S. Pat. No. 5,072,266. The device has a structure in which a central portion of the P base layer 3 extends deeper than the trench 5 does as shown in FIG. 52. Other structures of the device are the same as that of the background-art UMOS of FIG. 50.
When the drain voltage V.sub.DS is applied to the UMOS of FIG. 52, the depletion region extends from the P base layer 3 to the N.sup.- layer 2 in the same manner as the UMOS of FIG. 50. In the UMOS of FIG. 52, however, since the central portion of the P base layer 3 extends deeper than the trench 5, the equipotential lines form fewer loops at the tip end portion of the trench 5 and a gradual change of the equipotential lines can be found, from those which extend to an adjacent trench to those which enclose the trench 5. Accordingly, the discontinuity of the depletion region at the tip end portion of the trench 5 is relieved and the reduction in breakdown voltage of the device at the tip end portion of the trench 5 can be suppressed.
Furthermore, since the distance from the central portion of the P base layer 3 to the N.sup.+ substrate 1 is shorter than that from the tip end portion of the trench 5 to the N.sup.+ substrate 1, a breakdown occurs at the central portion of the P base layer 3 and the breakdown voltage is dependent on the central portion of the P base layer 3. Accordingly, even if the gate voltage V.sub.GS is reversely biased, it is possible to keep the breakdown voltage of the device from becoming lower by the reverse bias of the gate voltage V.sub.GS.
To ensure the required breakdown voltage of the device, however, in the device structure of the UMOS as shown in FIG. 52, the distance from the central portion of the P base layer 3 to the N.sup.+ substrate 1 should be long, that is, the N.sup.- layer 2 should be thick, since the central portion of the P base layer 3 extends deeper than the trench 5. In the case of the UMOS having a trench structure, a current path is found from the tip end portion of the trench 5 through the channel region 11 to the drain electrode in the ON state, and therefore the N.sup.+ layer 2 of greater thickness causes a higher On-resistance.
In the device structure of the UMOS as shown in FIG. 52, the trench 5 extends deeper than the P base layer 3 at a portion where the trench 5 and the P base layer 3 come into contact although the central portion of the P base layer 3 extends deeper than the trench 5. In order to form the P base layer 3, which is generally obtained by diffusion, the distance between the adjacent trenches 5 requires, at least, the sum of the length of an opening from which the impurity is implanted and twice the depth of the central portion of the P base layer 3, because the impurity is diffused over the same range in vertical and horizontal directions.
An evaluation of the spacing between the adjacent trenches on the basis of a commonly-used device size, assuming that the length of the opening at the central portion of the P base layer 3 is 2 .mu.m, the depth of the trench is 2 .mu.m and the depth of the central portion of the P base layer 3 is 3 .mu.m, determines the spacing L between the trenches to be about 8 .mu.m. As the spacing L between the trenches becomes larger than 8 .mu.m, the ON-resistance of the UMOS becomes higher. A test reveals that the ON-resistance becomes higher by about 0.18 .OMEGA.cm.sup.2 as a cell pitch (the spacing between the central portions of the adjacent trenches) becomes wider by 1 .mu.m.